1. Field of the Invention
The present invention relates, in general, to circuits and methods for recovering a clock signal.
2. Description of the Related Art
In general, a clock and data recovery (CDR) circuit provides a clock signal that is used to restore digital signals in a receiver stage of a high-speed data communication system such as an optical communication system, a backplane routing system and/or a chip-to-chip interconnect system, for example. The CDR circuit may recover a clock signal using a reference clock signal provided from a crystal oscillator, or alternatively may recover a clock signal without using a reference clock signal. When a reference clock signal is used to recover the clock signal, an external clock and a clock divider may be employed to generate a clock signal at a frequency equal to a frequency of a bit rate of input data. When the reference clock signal is not used to recover the clock signal, a frequency detector may be employed so as to directly extract frequency information from the input data.
In an example, a half-rate CDR circuit may be employed for high-speed data communication, which has half of a bit rate of the input data. When the half-rate CDR circuit is used, two phase-locked loops (PLL) may be employed to generate a half-rate quadrature clock signal, or alternatively one PLL may be employed to generate a half-rate quadrature clock signal. Using two PLLs may increase a chip area and also may increase power consumption. However, where one PLL is used, a voltage controlled oscillator (VCO) for generating a high frequency is required as the input data rate increases. Additionally, quadrature clock signals at the high frequency need to be transmitted to a receiving channel.
Thus, when the data rate is increased, the use of a single PLL configuration for a CDR circuit may lead to difficulties in designing a complementary metal oxide semiconductor (CMOS) of a PLL/VCO having low jitter characteristics. Moreover, as the clock signal is transmitted to respective channels, a mismatching effect and/or a coupling effect between transmission lines may be increased in proportion to the frequency of the quadrature clock signal. Moreover, power consumption of the transmission buffer may be increased.
In a conventional CDR circuit, one PLL may generate quadrature clock signals of 1.25 GHz, for example, and provide the quadrature clock signals of 1.25 GHz to a phase interpolator. The phase interpolator interpolates a phase of the quadrature clock signals in response to a feedback control signal and generates recovered 1.25 GHz clock signals. The recovered 1.25 GHz clock signals may be used to recover data.
The clock frequency output from the PLL and a recovered clock frequency may be the same. Thus, as the data rate increases to 8.5 Gbps, a PLL/VCO needs to generate an 8.5 GHz clock signal, and must transmit 8.5 GHz quadrature clock signals to the phase interpolator. A half-rate CDR circuit thus needs to transmit 4.25 GHz quadrature clock signals to the phase interpolator.
However, it may be difficult to implement a VCO which generates a frequency in excess of 8 GHz, and which simultaneously satisfies operational reliability, based on the present CMOS technology. Therefore, as data rate increases, it may be difficult to design a low jitter CMOS in a PLL, as mismatching and coupling effects among the clock transmission lines may be increased, and/or because power consumption may increase.
Moreover, where an integrated circuit (IC) for transceiving high-speed data adopts a multi-channel serializer/deserializer (SERDES), a multi-channel clock transmission line for transmitting a high frequency clock signal of a PLL to multiple channels is required. If multi-channel clock transmission lines are required to be designed, the IC adopting the SERDES may also be subject to mismatching and coupling effects among the transmission lines. Additionally, the IC with SERDES may have excessive power consumption in one or more transmission buffers thereof.
Another conventional CDR circuit may include a plurality of PLLs in an effort to reduce the number of transmission buffers, and so as to shorten a length of a transmission line. However, the conventional CDR circuits with multiple PLLs may have a downside in that such a configuration may require greater chip area. Additionally, circuit power consumption may be increased in proportion to the number of PLLs therein.